The present invention relates generally to the field of digital signal processing circuitry, and more particularly to the field of electronic ignition control systems which utilize digital signal processing circuitry for controlling spark and dwell occurrence.
In internal combustion engines the time occurrence at which a spark is produced to ignite a fuel and air mixture in a cylinder is a primary operational consideration. Similarly, producing an appropriate excitation signal (dwell) for an ignition coil immediately prior to the coil producing spark ignition is also a major design consideration. Mechanical spark control ignition systems have been found not to be reliable over long periods of time thus necessitating frequent readjustment of the mechanical controls. Thus electronic spark control ignition systems having greater reliability have been developed.
The majority of the prior art electronic spark timing control systems have been analog systems since those systems are typically more readily implemented with standard components. One such analog ignition control system is illustrated in U.S. Pat. No. 4,104,997, assigned to the same assignee as the present invention. In this analog electronic spark ignition control system, it is pointed out how controlling the rates of increase and decrease of an analog signal, which charges and discharges a capacitor, can result in producing a desired spark timing versus engine speed characteristic for an engine utilizing a distributorless ignition system. The term "distributorless" is utilized to indicate that the occurrence of spark ignition in different cylinders is not dependent upon the mechanical position of a standard distributor which channels spark energy to appropriate cylinders, but that spark ignition for each of the cylinders is determined by electronic switching circuitry.
The analog spark control system referred to above has the disadvantage that in accurately controlling the charge and discharge slopes of a capacitor in order to accurately determine spark timing, a number of precise individual settings of analog controls must be accomplished. This adds to the complexity and cost of the analog spark timing control system.
Digital spark control systems are known, and one such digital system is illustrated in copending U.S. patent application Ser. No. 779,974 filed Mar. 22, 1977 and entitled "An Electronic Ignition Timing System Using Digital Rate Multiplication", assigned to the same assignee as the present invention, now U.S. Pat. No. 4,168,682. This digital ignition control system illustrates how digital circuitry including a binary rate multiplier, a read only memory (ROM) which supplies control signals to the binary rate multiplier and an accumulator which receives the output of the binary rate multiplier can be utilized to accurately determine ignition spark timing through the use of digital circuitry. This copending application utilizes the output of the ROM to totally control the rate multiplication of a rate multiplier solely as a function the input of the rate multiplier. Other engine variables such as engine vacuum pressure and engine temperature are utilized to produce different pulse trains which serve as inputs to the rate multiplier and therefore affect the inputs and outputs of the read only memory circuit. The effect of this is that a rather large read only memory circuit is required for the prior art engine control system illustrated in the copending application. The advantage of the copending application is that it requires a substantially smaller read only memory than previous digital engine control systems such as those shown in U.S. Pat. Nos. 3,738,339 and 3,749,073, both of which require extremely large read only memories since both contemplate using ROMs to perform a point by point table look up function in order to produce a desired non-linear spark timing control signal or count which determines the desired engine speed versus spark advance characteristic. The prior copending application minimizes the size of read only memories utilized in ignition control systems by implementing piece wise linear accumulation rates for a pulse accumulator wherein the aggregate count is a complex function of engine speed and other engine variables. The present invention provides improved circuitry for reducing the size of the read only memory still further while producing an aggregate count related to several engine variables including engine speed and engine vacuum pressure.
Electronic dwell circuits for ignition control systems are known and U.S. Pat. Nos. 3,908,616 and 4,018,202 illustrate digital circuits for determining a dwell control signal. While the circuits shown in these patents evidently produce accurate digital dwell control signals, generally they are not economically adaptable to operate in conjunction with digital spark timing circuits in which the spark timing is to be a function of engine speed and other additional engine variables. Some prior dwell circuits (e.g. U.S. Pat. No. 3,908,616) cannot produce large dwell angles required at high engine speeds. Other prior dwell circuits such as U.S. Pat. No. 4,018,202 require complex feedback circuits having marginal stability.
Digital signal processing circuits exist which utilize a rate multiplier which is followed by an accumulator wherein the signal modification provided by the rate multiplier is controlled by a control means. In order to accomplish this signal modification in accordance with an analog signal, these prior art circuits convert each analog signal magnitude into a corresponding fixed digital word which serves as the input to a read only memory whose output serves as the control for the rate multiplier. If the output of the rate multiplier is desired to vary as the analog signal varies slightly in its magnitude (thus requiring high resolution analog to digital conversions), then an extremely large capacity read only memory device must be utilized since a different digital output from the read only memory must be produced in accordance with each minor analog signal magnitude variation for which a ROM output change is desired. The present invention minimizes the size of a read only memory in the above described processing circuit while permitting an extremely high resolution analog to ROM digital output conversion to be implemented. The manner in which this is accomplished is described in the remaining portions of this document.